SK Hynix and Intel explore shared memory pools to ease AI bottlenecks
SK Hynix is working with Intel on shared memory pool technology to address memory bottlenecks in agentic AI systems, presented at the Intel AI Summit in Seoul on November 12, 2026.
The memory maker's rack-scale design aims to let multiple AI servers draw from one large pool of memory as agentic AI workloads grow. This approach moves high-capacity memory into dedicated racks that multiple GPU and CPU servers can access through high-speed interconnects like Compute Express Link (CXL) and RDMA.
Performance improvements
The design specifically targets the KV cache problem, which grows quickly during multi-turn inference in AI models. SK Hynix's internal testing showed that using remote CXL DRAM from a shared pool reduced the average time to first token from 80.76 seconds to 15.45 seconds.
That works out to approximately an 81% reduction in first-token latency.
Continued partnership
This collaboration builds on the companies' previous work in server memory. In December 2025, SK Hynix became the first vendor to receive Intel Data Center certification for a 256 GB DDR5 RDIMM on the Xeon 6 platform, which delivered up to a 16% increase in inference performance and cut power consumption by approximately 18%.
SK Hynix Vice President Joo Young-pyo highlighted inefficiencies in traditional approaches where high-bandwidth memory is attached directly to each GPU. The shared memory pool architecture will be validated with Intel, customers and other strategic partners starting from the system-design phase.
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