AMD launches Zen 6 Venice Based Epyc CPUs - Semiaccurate
AMD has launched its new Zen 6 Venice-based Epyc CPUs, featuring up to 256 cores per socket with significant architectural changes since the Naples generation.
AMD has launched its new Zen 6 Venice-based Epyc CPUs, featuring up to 256 cores per socket with significant architectural changes since the Naples generation. The new platform represents the biggest architectural change in AMD's server architecture since 2018, when Rome was introduced.
The Venice architecture maintains the basic hub-and-spoke design with a central I/O Die (IOD) and Core Complex Dies (CCDs), but introduces two IODs per socket instead of one. This change was necessary to accommodate the increased number of DDR5 memory channels and high-speed CCD links.
Platform Variants
AMD is offering four main variants of Venice. The SP7 platform is the dual-socket beast supporting up to 256 cores and 16 DDR5-8000 channels. The SP8 platform uses a smaller package with only eight DDR5 channels but allows two DIMMs per channel. Verano is the LPDDR5x variant using SOCAMM modules, while Venice-X features stacked cache on each CCD.
The standard Venice SP7 CPU features two central IODs and eight 32-core CCDs, arranged to optimize space and thermal management. AMD also offers a 96-core Venice-F variant using eight smaller 12-core CCDs with higher clock speeds and different core characteristics.
Architectural Innovations
The most significant architectural change is the replacement of SERDES with EFB (Elevated Fan-Out Bridges) to connect chiplets. This silicon-to-silicon connection reduces power consumption and die size compared to the previous approach that used organic packaging with SERDES for long-distance data transmission.
The dual IOD design allows for better pin allocation, with DRAM pins on the shorter edges and high-speed D2D links on the longer ones. This layout would have been impossible with a single die given the 16 memory channels and 8 CCDs requiring significant bandwidth.
This isn't to criticize what AMD did, they appear to have done the right thing for the right reasons here, it saves power and die area which will pay big dividends on the TCO side.
Connectivity and Performance
SP7 supports two or three Infinity Fabric links between sockets, which can be configured as additional PCIe 6.0 slots when using two links. SP8 only supports two links. Both platforms use Gen 5 Infinity Fabric running at 64Gbps, the same speed as PCIe 6.0, allowing AMD to reuse the physical layer for efficiency.
The new CPUs offer improved power efficiency with power ratings ranging from 220W to 600W, though AMD has not fully disclosed all SKU details. The company listed 32 SKUs across SP7 and SP8 platforms, including 19 general parts, 8 high-frequency -F variants, and 5 single-socket SKUs, though complete specifications remain limited.
While AMD hasn't announced Threadripper variants for this generation, the architecture suggests a single-IOD CPU could eventually be developed. The Verano platform for LPDDR5x memory was only partially detailed at launch, with AMD promising more information in the future.
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