AMD ships 2nm Venice server chips, enterprise SP8 platform due in 2027
AMD has begun shipping its sixth-generation EPYC 9006 series processors, built on TSMC's 2nm process, with an enterprise socket SP8 platform expected in early 2027.
The Venice SP7 processor, featuring AMD's Zen 6 architecture, began shipping on November 10, 2026. These chips mark the first high-performance computing processors to reach production using TSMC's advanced 2nm manufacturing process. The top configurations offer impressive specifications with up to 256 cores and 512 threads, targeting dense agentic AI, cloud, HPC, and general enterprise workloads.
Memory bandwidth reaches up to 1.6 TB/s, and the chips support PCIe 6.0 technology. Major OEMs and ODMs have already begun shipping systems built around Venice, with over 240 server platforms committed to the architecture—a 20% increase over the previous Turin generation.
Cloud and Enterprise Roadmap
On the cloud side, both Azure and Oracle are expected to offer Venice-based instances soon. AMD is also preparing an enterprise-focused SP8 socket, scheduled for release in the first half of 2027. This platform will target mainstream business servers rather than the largest data center deployments.
Performance and Expansion
AMD's Venice-X variant targets HPC applications using advanced 3D V-Cache technology, which stacks extra memory directly on the chip. A separate design called Verano focuses on lower power consumption and LPDDR memory configurations. The Venice production ramp began earlier in 2026 in Taiwan, with AMD planning future expansion at TSMC's Arizona facility.
The company's data center segment revenue rose 97% year-over-year in Q3 2026 to a record $8.5 billion, driven by strong demand for both EPYC processors and Instinct GPUs. This growth underscores AMD's competitive position in the high-performance computing market.
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