AMD says Zen 6 delivers more CPU cores and L3 cache than Zen 5, plus greatly improved instructions per clock - Club386

AMD unveiled the details of its new Zen 6 microarchitecture during a launch event in Las Vegas, marking the debut of the 6th-generation Epyc server processors.

The company highlighted a 27% average improvement in instructions per clock (IPC) over Zen 5, a figure derived from a 20% gain in enterprise workloads and a 31% increase in AI performance.

This performance jump is particularly notable as it compares Zen 6 to the Zen 5c denser core design, rather than the standard Zen 5.

Core count and cache increases

Zen 6 core complex dies (CCDs) can now hold up to 12 cores, a 50% increase over Zen 5, with the Zen 6c variant supporting up to 32 cores.

This allows for a potential flagship desktop processor with 24 cores and 48 threads, while mid-range models could offer 12 cores and 24 threads.

L3 cache has also been expanded, with a maximum shared pool of 48MB per CCD and up to 128MB per CCD in Zen 6c designs.

Clock speeds and future timeline

Zen 6 Epyc processors feature a 300MHz clock speed increase, with a maximum frequency of 5.3GHz.

If these gains translate to consumer chips, the first Ryzen processors to hit 6GHz out of the box could arrive soon.

More details on the consumer Ryzen implementation, currently codenamed Olympic Ridge, are expected in 2027, with CES being a likely venue for an announcement.