AMD's 'Zen 6' Architecture Detailed: EPYC Data Center Chips Get Dibs, But Ryzens Might Benefit, Too - PCMag Middle East

AMD is leveling up its Zen microarchitecture to power the next generation of its EPYC enterprise processors. The forthcoming Zen 6, outlined in deep detail for the first time, transitions EPYC to a cutting-edge 2nm manufacturing process and includes architectural improvements aimed at boosting performance and bandwidth.

The information AMD has provided shows an improved architecture that can keep more data in flight than Zen 5. The most important change is that Zen 6 enables higher-than-ever core counts, which will likely flow down to all upcoming AMD processors that employ the new microarchitecture.

For readers in the UAE, Saudi Arabia, and Egypt, Zen 6 is a data center story before it is a gaming one. The EPYC Venice server parts will reach enterprise buyers first. Consumer Ryzen chips built on the same core come later, and at the time of writing no regional pricing or local availability has been published.

Core Design Evolution

A key change is that Zen 6 will enable packing 12 cores into each chiplet. With its debut in AMD's next-gen EPYC server chips, code-named Venice, that can scale to a staggering 256 cores. It also sets the stage for eventual higher-core-count Ryzen desktop processors.

AMD is producing its latest CPU core in two slightly different designs this time: Zen 6 cores are the full version, while Zen 6c cores are more compact. Based on the information available, the 6 and 6c cores are the same, except that the Zen 6c cores are smaller.

With AMD's Zen 4 and Zen 5 architectures, this was achieved by reducing the size of L3 cache. Zen 4c and Zen 5c processor cores had only half the L3 cache of their Zen 4 and Zen 5 counterparts. With Zen 6c, however, AMD added 4MB of L3 cache per core, exactly the same as it provides for Zen 6 cores.

Performance Improvements

Based on the details AMD provided, Zen 6 and Zen 5 are very similar in many aspects of their design. The L1 and L2 caches are unchanged, as are the decoding hardware, the dispatch unit, the floating-point unit, and most of the execution hardware.

Zen 6 has one less multiplication unit (MUL unit) than Zen 5, which is replaced with a division unit (DIV unit). Zen 5 didn't have a DIV unit, which likely improves performance in specific scenarios.

Both Zen 5 and Zen 6 have six arithmetic logic units (ALUs) in each core, which handle simplified operations broken down from complex instructions. This design approach allows processors to perform work using more basic computational elements.