CUDA 13.5 Makes Vera Rubin Production-Ready: NVIDIA Expands Scheduling and Multi-GPU Communication - igor´sLAB

The update enables developers to prepare production software for Vera Rubin with a regularly supported CUDA version.

Administrators can now connect cgroup-v2 structures with Multi-Process Service namespaces, allowing workloads to be automatically assigned different resource policies.

Per-namespace Streaming Multiprocessor partitions are also new, specifying which SM partition a particular namespace is allowed to use for each device.

This is particularly useful in shared GPU systems, where multiple services or users share a single accelerator instance.

NVIDIA is also adding polling-based memory monitoring for cases where cgroup notifications about memory limits are unavailable or do not arrive reliably.

MPS can then query current usage directly before deciding whether to evict a process or release resources.

Support for batched one-dimensional copy operations is being added for CUDA Graphs, allowing cudaMemcpyBatchAsync to be captured during stream recording.

Applications with many smaller transfers can thereby reduce their CPU-side management overhead.

Direct Multi-GPU Communication

The change is more substantial with CUDA Tile, which enables direct access to memory on another GPU connected via NVLink from within a Tile kernel.

Unicast pointers address a single neighboring device, while multicast pointers and special multimem operations can distribute or reduce data across NVSwitch fabrics.

This makes it possible to bring communication and computation together more closely within the same kernel.

NVIDIA cites combined matrix multiplications and cross-GPU reductions as examples.

Such workloads occur, among other contexts, with large AI models whose tensors are distributed across multiple accelerators.

Fewer separate kernel launches and fewer intermediate copies can reduce latency and synchronization overhead in these cases.

CUDA Tile also receives a preview of interoperability with conventional SIMT code.

Tile kernels can directly call device functions from SIMT libraries while data is already in registers or shared memory.

Until now, corresponding components had to be connected through separate kernels and global memory.

Math Libraries and Driver Model

The math libraries have also been adapted for Vera Rubin.

cuBLAS adds new heuristics and kernels for NVFP4 and MXFP8 matrix operations, including for typical Mixture-of-Experts workloads.

For Blackwell, NVIDIA cites improvements of up to 1.5× for certain native FP64 SYRK and HERK operations, while cuSPARSE promises significantly larger gains depending on the algorithm.

These figures apply to specific library operations and should not be interpreted as general GPU acceleration.

Rubin also brings a change to the driver model on Windows.

CUDA supports WDDM and Microsoft’s Compute Driver Model (MCDM), while TCC is no longer supported on Rubin and subsequent GPU generations.

Software that has so far depended on TCC must therefore be adapted for future platforms.

Infrastructure for Large Systems

CUDA 13.5 is interesting less for individual percentage figures than for the infrastructure it provides for Vera Rubin.

NVIDIA is moving more resource management and multi-GPU communication directly into CUDA and CUDA Tile.

This allows large accelerator systems to be partitioned more finely and communication steps to be more closely integrated with computation.

Many of these features are secondary for consumer graphics cards, but directly relevant to data centers and AI systems.