NVIDIA has closed the option to remove hardware limits for tensor cores in the GeForce RTX 50 series. - GameGPU
NVIDIA has closed the option to remove hardware limits for tensor cores in its GeForce RTX 50 series graphics cards, a feature that was possible on previous generations.
NVIDIA uses the same GPU dies for both consumer and professional GPU lines but artificially limits the performance of Tensor Cores when executing FP32 accumulation operations on consumer models. This limitation affects Turing, Ampere, and Ada Lovelace series, where hardware fuses are blown during manufacturing, reducing processing speed for certain formats.
Previous Vulnerability
A buffer overflow vulnerability in the signed Booter microcode of the SEC2 security microcontroller previously allowed users to lift these restrictions on architectures up to Ada Lovelace. This exploit increased the base speed of corresponding instructions from 165 to 331 TFLOPS on the GeForce RTX 4090.
Enhanced Security
On Blackwell-generation consumer graphics cards, including the RTX 50 series, NVIDIA has fundamentally changed the security architecture. The hardware root of trust is now the RISC-V-based FSP security processor, which boots from its own read-only memory before accessing the driver.
The Booter microcode of the SEC2 microcontroller is completely excluded from the initialization chain, and the firmware is encrypted with RSA-3K cryptographic signatures. Critical code is compiled using the SPARK language, which eliminates runtime memory overflow errors and closes the attack vector.
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