Nvidia and SPIL plan 15x expansion of co-packaged optics capacity by mid-2027

At Nvidia's GTC Berlin event, CEO Jensen Huang announced that optical networking in AI data centers could drive demand for optical components up by 15 times by mid-2027, with a further expansion to 30 times by the end of 2028. This ambitious plan reflects the strain current interconnect technology faces under modern AI workloads.

As AI models grow larger and data centers pack in more accelerators, cables and connectors linking chips together have become a genuine bottleneck. Copper connections, which have handled this job for decades, are encountering physical limits around power consumption, signal degradation, and bandwidth density.

Co-packaged optics technology

The expansion centers on co-packaged optics (CPO), which integrates optical engines directly alongside silicon rather than connecting them externally. This approach cuts signal travel distance and improves both power efficiency and signal integrity.

Nvidia is introducing its Spectrum-6 CPO switches as the flagship product built around this architecture, designed specifically for its Vera Rubin AI factories. These switches promise higher bandwidth density and reduced energy consumption compared to existing networking gear.

Broader manufacturing investments

The optical capacity expansion is part of a larger investment picture. Nvidia has committed $1.1 billion to advance US semiconductor testing capacity through a partnership with KYEC, with production targeted to begin in April 2027.

Separately, packaging partner Amkor plans to grow its interposer wafer production capacity by over 300% by the end of 2028. Interposers allow multiple chiplets to connect at high speed within a single package, indicating strong confidence in continued demand growth.

Why optical now

The shift from copper to optical interconnects has been discussed for years, but recent economic and engineering advances have made large-scale deployment practical. AI training clusters, which link thousands of accelerators, have accelerated this timeline considerably.

CPO represents a further refinement by reducing the electrical path between chip and fiber, cutting latency, and improving power efficiency. Huang's prediction reflects Nvidia's infrastructure requirements rather than abstract market forecasts, with manufacturing partnerships already lined up to achieve these goals.